This is the prototype of Multithreded ARM Processor with 4-Kbytes Embeede SRAM.
Before integrating to Single-Chip Programmable Platform, it was evaluated as a separated chip. It can store four context with the individual register file and switch among the context very fast.
Layout of the Multithreaded ARM Processor
ARMISS (ARM Instruction Set Simulator) is developed for ARM7/ARM9 Compatible Processor Design.
ARMISS can run the binary image file from ARM compiler for compatibility test.
ARMISS is a cycle-accurate simulator to validate accurate pipelined operation and it also can be compiled to BFM (Bus Functional Model) for a System-on-Chip design.
It saves simulation time as it is hundred times the faster than Verilog RTL Simulation.
SoftARM is Graphic User Interface based on GTK+ (The GIMP Toolkit) which is connected to ARMISS through ARMISS via IPC (Inter-Process Communication). SoftARM also can be connected to Verilog Simulator via IPC to control and monitor the simulation.
In 1999, I led a project to develop the embedded processor design technology with the sponsorship of Korea Ministry of Science and Technology, Korea Ministry of Commerce, Industry and Energy.
In order to catch up the state-of-art technology, I designed the ARM7TDMI compatible processor first.
The behavioral compatibility is verified by developing the instruction set simulator, ARMISS and
prototyping with FPGA.
It was integrated to RamP processor which using the MML (Merged Memory Logic) process.
As the MML process is not developed for the commercial usage, there was no standard cell library. I developed not only the processor but also the standard cell library for it with the technology that I developed for IDEC library.
FPGA Prototype of ARM7 Compatible Processor
Die Photo of ARM7 Compatible Processor
In the late 90′s, there was a long-term project named as MICROS (Micro Information and Communication Remote Object-oriented Systems) for developing a very small-sized wireless system with ultimate low-power consumption to put into human body finally.
For the fundamental technology development for wireless communication, I designed the baseband processor for wireless LAN system.
It was very good chance to understand synchronization mechanism and packet processing and It gave huge inspiration when I was developing high-speed interface later.
Young-Don Bae (www.donny.co.kr)
Based on the technology developed IDEC Library, a formal environment was developed for over 400 cells on 0.25um CMOS technology.
It generates Synopsys Synthesis Library and Verilog Simulation Library from a common functional description and automatically characterize the timing information by generating HSPICE routines.
I designed two test vehicle for evaluation. One of them was fabricated for function test and the other for timing characteristics test.
I was involved into that project for developing Standard Cell Libary for IDEC(IC Design Education Center).
Professor Kyung founded IDEC in 1994 and managed MPW(Multi-Project Wafer) for students can have the chance to design chips. However, there was significant limitation that they only possible to design very simple circuits as the foundry company did not provide Standard Cell Library for the confidential reasons.
Standard Cell Library is a group of basic logic circuits including AND-gate, OR-gate and inverters that is ready-made to synthesis complex system chips. In order to synthesize a design, the schematic, function, timing characteristics and layouts are designed and registered to CAD softwares including Synopsys DesignCompiler, Cadence Verilog Simulators and P&R tools such as Astro.
For those reasons, IDEC had decided to develop the own Standard Cell Library. As there is very little information for library development at that time, however, there was too little progress for almost a year. Then I was involved as a troubleshooter and I reported the dramatic progress at the weekly project meeting every time.
One of the most serious problem is P&R(Place & Route). There were the functional issues and availablity issues due to the limited license. After several months, I all cleared the problem and wrote User’s Manual make CDs for distribution. The name of the library was named as IDEC-C631 which means CMOS 0.6um Triple Metal library.
The test vehicle for validate the library was a microprocessor, MISC (Minimal Instruction Set Computer). Dr. Park wrote the verilog code and I synthesized it into the layout with IDEC-C631 library. If the one of schematic, layout, function and timing description for a single cell among the total 100 cells has a mistake, the chip would not operate. However, the results are very successful.
It is the first microprocessor that has my name on it.
MISC프로세서의 Die Photo
Young-Don Bae (www.donny.co.kr)
반도체와 처음 인연을 맺은 것은 1995년 겨울이었다.
당시 학부 3학년이었던 나는 졸업 후 석사과정에 진학하여 DSP(Digital Signal Processor)를 설계해보라는 교수님의 독려도 대학원 연구실에 들어가게 되었다. 줄곧 공부와 담 쌓고 컴퓨터 프로그래밍에만 빠져있다가 뒤늦게 진학을 생각하고 전공필수과목을 재이수 하고있던 내겐 매우 의아하면서도 놀라운 제안이었다.
반도체회사에 계시다가 오신 교수님께서는 넘치는 열정으로 연구실을 셋업하시는 중이었고 4학년 선배 3명과 3학년 2명을 뽑으셨다. 3학년 중에 나보다 공부잘하는 친구들이 많았는데 (사실 나보다 학점 낮은 학생이 별로 없었다. ㅡㅡ;) 왜 날 선택했는지는 아직도 미스테리이지만 (그때는 교수님께서 사람 보는 눈이 있으시다고 생각했었다 ^^;;) 추측해보면 프로그래밍을 잘하는 사람이 반도체설계를 잘할 것이라는 믿음때문이었던 것 같다.
아무래도 학점 높은 학생이 똑똑하다고 생각할텐데 그런 고정관념을 깨고, 게다가 아날로그회로설계를 하시던 분이 그런 생각을 하셨다는게 참 놀랍다.
당시 설계한 칩의 구조
어찌되었건 그렇게 시작하여 1년 선배였던 종필이형과 GPS 수신기 칩셋 중 Digital Correlator라고 하는 칩을 설계하였다. FPGA에 프로그래밍하여 실제 시스템에서 연동해보고 다시 실리콘으로 만들었다. IDEC MPW(Multi Project Wafer) 삼성 0.8um SOG(Sea-of-Gate)를 이용하였고 5mmx5mm의 크기였다.
이제는 수많은 GPS 내비게이터에 사용되는 SiRF칩의 일부에 해당하는 기능 뿐이고, Reference 제품의 Spec을 보고 모방했던 제품이었으나, 실제 통신시스템에 사용되는 칩셋을 개발하면서 통신시스템의 기본 개념을 익힐 수 있어 지금까지도 큰 도움이 되고있다. 또한, GPS의 기본원리인 Spread Spectrum방식은 CDMA 통신방식의 기본이기 때문에 통신시스템에 대해 꾸준한 관심을 갖게 해준 소중한 경험이었다. 생각해보면 지금 핸드폰용 반도체를 만드는 것도 또 고속인터페이스를 만드는 것도 모두 연장선상에 있는 일들이다.
2008.8 배영돈 (www.donny.co.kr)