MagnaChip Accelerates Advancement into Smart Phone Driver IC Market
The leading provider of analog and mixed signal semiconductor products, unveils a full scale to advance
the market of display driver chips for smart phones. They started allocating driver IC for smart phones to a Korean-based major ‘A’ mobile phone maker earlier this year.
smart phone equipped with MagnaChip’s AMOLED driver chip was been recognized as an excellent product optimized for functions and capabilities of smart phones.
MagnaChip’s display driver chip for smart phones supports 16 million colors with WVGA resolution and uses the next generation technology of automatic current limit (ACL) and MIPI display serial interface (DSI), which are a good match for smart phones.
As for the vice president of MagnaChip, Hwang Tae-Young that MagnaChip intends to improve its driver chip technology and grow its market power by making a timely supply of high-quality products that are differentiated from the products of its rivals.
and early on, smart phone market is forecast to make a rapid growth of 46 percent per year by 2012.
MagnaChip Semiconductor announces WVGA resolution supported AMOLED driver chip ? EA8850
A company from Korea called MagnaChip Semiconductor has just announced the EA8850, a new high-end WVGA resolution supported AMOLED driver chip that would give way to more high resolution handsets in the mobile market.
The EA8850 supports WVGA (480RGB x 864) resolution, and at the same time it also works with nHD (360RGB x 640) resolutions. It also supports Qualcomm’s Mobile display digital interface (MDDI) 1.2 technology.
Other features that you might take for granted about the MagnaChip Semiconductor EA8850: support for 16 million colors, automatic brightness control and smart mobile current control.
It wasn’t specified when the Korean company plans to supply this AMOLED driver chip to handset makers, but it should be present in devices that are to be released later this year.
TFT LCD Driver integrates MIPI and DSI on one chip.
August 12, 2008 – Suited for use in mobile phone displays, TA8560 combines MIPI (Mobile Industry Processor Interface) and DSI (Display Serial Interface) onto one driver chip. DSI, based on scalable serial interconnect, provides lower power modes and allows bi-directional communications. It supports 16-, 18-, and 24-bit pixels, buffered and un-buffered display panels, and QVGA (240 x 320) resolution. Chip can drive up to 4 panels from 1 interface and displays up to 16 million colors.
MDDI (Mobile Display Digital Interface) is Qualcomm’s technology for high-speed serial interface between their MSM (baseband) chip and the peripheral including display module and camera module.
In 2006, I leaded the development of MDDI IP (Intellectual Property) including analog PHY and logic core.
The IP is successfully evaluated to 300Mbps for a data lane and supports dual display.
I designed my own MDDI logic core that receives 4-bit wise parallelized data and extract packets containing commands and display pixel data and transfer it to various legacy interfaces for the straightforward integration.
It requires only 30% area of Qualcomm’s original MDDI core nonetheless it has the almost the same features.
Working with Qualcomm people was good experience and I still working on MDDI 1.2 with them.
Since 2005, I have started development of LCD Driver ICs.
With my first product I achieved 25 million sales until now.
I leaded the design and verification for all the logic inside the driver IC such as Timing Controller, Memory Controller and CPU Interface.
Until now I participated 12 projects and many of them is under the mass production.
In the year 2004, I presented the paper entitled “A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors” at IEEE CICC (Custom Integrated Circuit Conference) in 2004.
CICC is the second biggest conference after ISSCC (International Solid-State Circuit Conference) for the chip designers.
Now the dual-core and quad-core is available at the market. Integrating nine processors including a multi-threaded processor on a single die is very aggressive challenge at that time.
The aim of the chip is implementing a system chip just by software programming.
The IO processors are dedicated to process concurrent IO behavior. SIMD(Single Instruction Multiple Data) processors process the media (video or audio) applications in parallel and multhreaded processor processes concuffent system behavior with fast context switching.
Die Photo of Single-Chip Programmable Processor Array
In the year 2003, I and SSL team presented “A 210mW Graphics LSI implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications” at ISSCC (International Solid-State Circuit Conference)
I designed the 5-stage RISC processor with 8KB Instruction and Data Cache for 3D geomery processing and founded the full-chip integration flow with automatic P&R with Apollo (now it is Astro).
Die Photo of RamP-IV
Microscopic signature on the chip.
RamP-IV is the world first all-in-one 3D graphic processor for mobiel application and successfully demonstrated displaying on VGA display on the prototype system.
Ramp-IV Evaluation Environment
Ramp-IV Evaluation Environment (Revised)
Multithreaing was one of the hottest issues at the ISSCC 2002 as two papers in the microprocessor session newly employed multithreading at the same time.
As it was a year before Intel announced to introduce Hyper-Threading, multithreading was brand-new technology for industries at that time.
As the impact of ISSCC is very huge, they didn’t hesitate to say Multi-threading “rules”.
In the year 2002, I presented the paper about the multithreaded processor incorporating configurable logics at ISSCC (International Solid-State Circuit Conference).
Until then multithreading was just one of the concepts in the papers or textbooks. I adapted the multithreading concept to ARM processor to enhance concurrent control for complex behavior for system chip and configurable logics for implement dedicated hardwares.
The block names as CLC (Configurable Logic Cluster) is a type of FPGA (Field Programmable Gate Array) for ASIC foundry. I designed the architecture for programmable logic including routings and look-up tables, drew the layout and ported it to P&R software by myself.
Die Photo of Single-Chip Programmable Platform
It was the great honor for me as it is the first paper presented in the microprocessor session in ISSCC for my mother country. It is very obvious how it is hard to present a paper for its microprocessor session if you have a look on the program book below as all the papers came from industry top companies including Compaq, Sun, IBM, Intel, Hewlett Packard.
The picture above was taken after the rehearsal at the day before the conference with the chairman, co-chairman and other speekers for the same session. The co-chairman was Simon Segars, Executive Vice President of ARM Ltd. As I was involved in the ARM compatible processor development project for years, I read his articles many times and my design is also based on ARM architecture. So it was very nice to see him and very challenging to rehearse in fromt of him.
In the year 2001, I published a paper entitled “A 80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM” describing about the 2nd-generation RamP.
It integrates MPEG-4 accelerator, 3D Rendering Engine, ARM9 compatible RISC processor with enhanced MAC and the integrated DRAM frame buffer for Mobile Applications.
As the full-chip integration was done manually at that time, the floorplan is not that fancy.
It was, however, still great work to be carried in university.
The microscopic signature on the chip.