In the year 2004, I presented the paper entitled “A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors” at IEEE CICC (Custom Integrated Circuit Conference) in 2004.

CICC is the second biggest conference after ISSCC (International Solid-State Circuit Conference) for the chip designers.

Now the dual-core and quad-core is available at the market. Integrating nine processors including a multi-threaded processor on a single die is very aggressive challenge at that time.

The aim of the chip is implementing a system chip just by software programming.
The IO processors are dedicated to process concurrent IO behavior. SIMD(Single Instruction Multiple Data) processors process the media (video or audio) applications in parallel and multhreaded processor processes concuffent system behavior with fast context switching.

Die Photo of Single-Chip Programmable Processor Array

In the year 2003, I and SSL team presented “A 210mW Graphics LSI implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications” at ISSCC (International Solid-State Circuit Conference)

I designed the 5-stage RISC processor with 8KB Instruction and Data Cache for 3D geomery processing and founded the full-chip integration flow with automatic P&R with Apollo (now it is Astro).

Die Photo of RamP-IV

Microscopic signature on the chip.

RamP-IV is the world first all-in-one 3D graphic processor for mobiel application and successfully demonstrated displaying on VGA display on the prototype system.

Ramp-IV Evaluation Environment

Ramp-IV Evaluation Environment (Revised)

In the year 2002, I presented the paper about the multithreaded processor incorporating configurable logics at ISSCC (International Solid-State Circuit Conference).
Until then multithreading was just one of the concepts in the papers or textbooks. I adapted the multithreading concept to ARM processor to enhance concurrent control for complex behavior for system chip and configurable logics for implement dedicated hardwares.

The block names as CLC (Configurable Logic Cluster) is a type of FPGA (Field Programmable Gate Array) for ASIC foundry. I designed the architecture for programmable logic including routings and look-up tables, drew the layout and ported it to P&R software by myself.

Die Photo of Single-Chip Programmable Platform

It was the great honor for me as it is the first paper presented in the microprocessor session in ISSCC for my mother country. It is very obvious how it is hard to present a paper for its microprocessor session if you have a look on the program book below as all the papers came from industry top companies including Compaq, Sun, IBM, Intel, Hewlett Packard.

The picture above was taken after the rehearsal at the day before the conference with the chairman, co-chairman and other speekers for the same session. The co-chairman was Simon Segars, Executive Vice President of ARM Ltd. As I was involved in the ARM compatible processor development project for years, I read his articles many times and my design is also based on ARM architecture. So it was very nice to see him and very challenging to rehearse in fromt of him.

This is the prototype of Multithreded ARM Processor with 4-Kbytes Embeede SRAM.
Before integrating to Single-Chip Programmable Platform, it was evaluated as a separated chip. It can store four context with the individual register file and switch among the context very fast.

Layout of the Multithreaded ARM Processor