마이크로프로세서 설계 무작정 따라하기 – Part 1

IDEC Newsletter에 2001년 6월부터 2001년 9월까지 연재한 내용입니다.

마이크로프로세서 설계 강좌를 연재하게 된 계기는 명확히 기억나지 않습니다만, 경종민교수님의 추천으로 시작한 것 같습니다. 경교수님께서 시스템칩 설계에 초심자들이 쉽게 접근할 수 있는 자료를 원하셨고, 당시 내장형 프로세서를 개발했던 제가 적임자로 지목되었던 것 같습니다.

3부작 정도로 계획했지만 결과적으로 2년간 총 14부의 장기 연재를 했습니다.
적지않은 시간을 투자했던 만큼 애착이 크도 또 아쉬움도 남습니다.

기본적이고 핵심적인 내용을 중심으로 했기 때문에 지금 반도체설계를 공부하시는 분들께도 도움이 될 것이라 믿지만, 이미 7년이란 시간이 흘러 개정판을 써보고 싶은 생각도 있지만 쉽지는 않을 듯 합니다.

1부 1편: 서론, 마이크로프로세서 개요, 명령어 구조, SimpleCore의 구조, Datapath RTL 설계

1부 2편: Datapath RTL 설계

1부 3편: Control 설계 (Fetch Unit, Decode Unit, Execute Unit, Pipeline)

1부 4편: 시뮬레이션 (Test Module, Verilog-XL), 맺음말

마이크로프로세서 설계 무작정 따라하기 – Part 2

1부의 반응이 좋아 추가 연재를 의뢰 받아서 IDEC Newsletter에 2001년 10월부터 2002년 2월까지 연재한 내용입니다.
2부는 개발환경 (명령어시뮬레이터, 컴파일러, 어셈블러) 개발에 대한 내용입니다.

2부-1편: 마이크로프로세서 개발 환경, 명령어 시뮬레이터

2부-2편: GNU C컴파일러(GAS), GCC 포팅과정 (컴파일러 Backend, 컴파일러 환경 설정)

2부-3편: GCC 포팅과정 (저장 영역의 레이아웃, 자료형, 레지스터, 스택구성, 주소지정)

2부-4편: GCC 포팅과정 (데이터전송, 산술연산, 비교/분기, 함수호출)

2부-5편: GNU Assembler(GAS) 포팅

마이크로프로세서 설계 무작정 따라하기 – Part 3

IDEC Newsletter에 2002년 4월부터 2002년 12월까지 연재한 내용입니다.

6년이 흘렀지만 개발환경에는 큰 변화는 없습니다. 여전히 합성을 위해 Synopsys Design Compiler를 사용하고 있고, P&R을 위해선 Apollo의 후속 버젼인 Astro를, 시뮬레이션은 Verilog-XL과 기능자체는 큰 차이없는 NC-Verilog를  사용하고 있습니다. 큰 차이는 없다고는 해도 그대로 따라할 수는 없기때문에 아쉬움도 있고 또 일부 내용은 개선하고 싶은 부분도 있네요.

3부-1편: 합성 가능한 설계 (Synthesiable Design)

3부-2편: 합성 (Synthesis), Synopsys DesignCompiler, 최적화

3부-3편: 순차회로의 최적화 (입/출력 지연시간, 홀드 타임, 클럭 버퍼링)

3부-4편: SimpleCore의 합성

3부-1편: 후단계 설계, Appllo를 이용한 SimpleCore의 P&R

ISSCC 2003 – RamP-IV

In the year 2003, I and SSL team presented “A 210mW Graphics LSI implementing Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications” at ISSCC (International Solid-State Circuit Conference)

I designed the 5-stage RISC processor with 8KB Instruction and Data Cache for 3D geomery processing and founded the full-chip integration flow with automatic P&R with Apollo (now it is Astro).

Die Photo of RamP-IV

Microscopic signature on the chip.

RamP-IV is the world first all-in-one 3D graphic processor for mobiel application and successfully demonstrated displaying on VGA display on the prototype system.

Ramp-IV Evaluation Environment

Ramp-IV Evaluation Environment (Revised)

CICC 2004 – Single-Chip Programmable Processor Array

In the year 2004, I presented the paper entitled “A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors” at IEEE CICC (Custom Integrated Circuit Conference) in 2004.

CICC is the second biggest conference after ISSCC (International Solid-State Circuit Conference) for the chip designers.

Now the dual-core and quad-core is available at the market. Integrating nine processors including a multi-threaded processor on a single die is very aggressive challenge at that time.

The aim of the chip is implementing a system chip just by software programming.
The IO processors are dedicated to process concurrent IO behavior. SIMD(Single Instruction Multiple Data) processors process the media (video or audio) applications in parallel and multhreaded processor processes concuffent system behavior with fast context switching.

Die Photo of Single-Chip Programmable Processor Array

ISSCC 2002 – Single-Chip Programmable Platform

In the year 2002, I presented the paper about the multithreaded processor incorporating configurable logics at ISSCC (International Solid-State Circuit Conference).
Until then multithreading was just one of the concepts in the papers or textbooks. I adapted the multithreading concept to ARM processor to enhance concurrent control for complex behavior for system chip and configurable logics for implement dedicated hardwares.

The block names as CLC (Configurable Logic Cluster) is a type of FPGA (Field Programmable Gate Array) for ASIC foundry. I designed the architecture for programmable logic including routings and look-up tables, drew the layout and ported it to P&R software by myself.

Die Photo of Single-Chip Programmable Platform

It was the great honor for me as it is the first paper presented in the microprocessor session in ISSCC for my mother country. It is very obvious how it is hard to present a paper for its microprocessor session if you have a look on the program book below as all the papers came from industry top companies including Compaq, Sun, IBM, Intel, Hewlett Packard.

The picture above was taken after the rehearsal at the day before the conference with the chairman, co-chairman and other speekers for the same session. The co-chairman was Simon Segars, Executive Vice President of ARM Ltd. As I was involved in the ARM compatible processor development project for years, I read his articles many times and my design is also based on ARM architecture. So it was very nice to see him and very challenging to rehearse in fromt of him.

ISSCC 2002 Press Release

Multithreaing was one of the hottest issues at the ISSCC 2002 as two papers in the microprocessor session newly employed multithreading at the same time.
As it was a year before Intel announced to introduce Hyper-Threading, multithreading was brand-new technology for industries at that time.
As the impact of ISSCC is very huge, they didn’t hesitate to say Multi-threading “rules”.