The $deposit system task allows you to set a net to a particular value and then to simulate
with the net set to that new value. The value change is propagated throughout the nets and
registers being driven by the variable that has been set. The syntax is as follows:
The $deposit task can be used within any Verilog-XL procedural block. You can define the time at which the net is to be given a new value using the standard procedural constructs. The task can also be used on the interactive command line.
Use this system task as a debugging or design initialization aid. You should not use it as a
representation of actual circuitry.
Common uses for the $deposit system task include the following:
- To initialize large portions or all of a circuit either at the beginning of or during a simulation. You can select the nodes to be deposited to yourself, or use PLI code to extract the node names.
- To stop the simulator during a debugging session and to use the command on the interactive command line to set a new value.
- To reset a circuit to a known state after simulation in order to retry a different debug route.
- To set parts of a circuit to analyze intricate circuit details (common for switch level simulation).
- To break feedback loops to set them to a known state.
In the syntax, variable is the name of the net or register whose value is being changed. The variable can be a net or register type but not a parameter, and it can be a vector or scalar object that can be expanded or compacted.
The second parameter, value, is a numerical or logical value in standard Verilog-XL notation. Bit and part selects are not allowed.
If the width of the value is smaller than the range of the variable, an error message is generated. If the width of the value is larger than the range of the variable, the MSBs are truncated and a warning is issued.
X and Z states can also be deposited.
Here are some examples of using $deposit:
p.s. 좋은 Tip알려준 yangk에게 감사.. ^^